This invention relates generally to non-volatile semiconductor memories of the flash EEPROM (Electrically Erasable and Programmable Read Only Memory) type, their formation, structure and use, and specifically to methods of making word lines and select lines in NAND memory cell arrays.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which use an array of flash EEPROM cells. An example of a flash memory system is shown in FIG. 1, in which a memory cell array 1 is formed on a memory chip 12, along with various peripheral circuits such as column control circuits 2, row control circuits 3, data input/output circuits 6, etc.
One popular flash EEPROM architecture utilizes a NAND array, wherein a large number of strings of memory cells are connected through one or more select transistors between individual bit lines and a reference potential. A portion of such an array is shown in plan view in FIG. 2A. BL0-BL4 represent diffused bit line connections to global vertical metal bit lines (not shown). Although four floating gate memory cells are shown in each string, the individual strings typically include 16, 32 or more memory cell charge storage elements, such as floating gates, in a column. Control gate (word) lines labeled WL0-WL3 and string selection lines, Drain Select Line, “DSL” and Source Select Line “SSL” extend across multiple strings over rows of floating gates. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard by placing a relatively high voltage on their respective word lines and by placing a relatively lower voltage on the one selected word line so that the current flowing through each string is primarily dependent only upon the level of charge stored in the addressed cell below the selected word line. That current typically is sensed for a large number of strings in parallel, thereby to read charge level states along a row of floating gates in parallel. Examples of NAND memory cell array architectures and their operation are found in U.S. Pat. Nos. 5,570,315, 5,774,397, 6,046,935, and 7,951,669.
The top and bottom of the string connect to the bit line and a common source line respectively through select transistors (source select transistor and drain select transistor). Select transistors do not contain floating gates and are used to connect NAND strings to control circuits when they are to be accessed, and to isolate them when they are not being accessed.
FIG. 2B is a circuit diagram for a portion of a NAND flash memory array such as shown in FIG. 2A. It can be seen that drain select line DSL controls select transistors at one end of NAND strings which connect to bit lines while source select line SSL controls the other end of NAND strings which connect to a common source line. It can be seen that select transistors have different functions and different structures to memory cells (e.g. select transistors have no floating gates). However, it is generally not desirable to use a different set of process steps for formation of select transistors and memory cells.
Thus, there is a need for a memory chip manufacturing process that forms the memory cells and select transistors in an efficient manner and there is a need for structures that can be formed accordingly.